1. Field of the Invention
The present invention relates to a circuit and method for overflow detection in a digital signal processor (DSP) having a serially connected barrel shifter and arithmetic logic unit (ALU). More particularly, the present invention relates to a DSP and overflow detection method which considers an operand output from the barrel shifter, an operand output by a code extender and a carry signal from the ALU to detect a positive or negative overflow condition without degrading the performance of the DSP.
2. Description of the Prior Art
FIG. 1 shows an example of a conventional DSP in which a barrel shifter is serially connected to an adder. Inside a typical high-speed DSP, a barrel shifter 11 is generally connected in series with an ALU having a modified form of the adder as indicated in FIG. 1. If the serially connected barrel shifter 11 and ALU are used during a single operational clock cycle, an overflow condition may be generated. Usually, an overflow detector 15 is used to provide for the case where the sign of the overflow result is changed during the occurrence of an overflow event.
Generally, the overflow detector 15 generates a maximum value within an effective number range of the DSP of FIG. 1 when a positive overflow is generated and generates a minimum value when a negative overflow is generated. Therefore, it is desireable that the overflow detector 15 detect the overflow condition and output the appropriate value within a short time period so as not to lower the performance of the DSP.
In the circuit of FIG. 1, if barrel shifter 11 is not present, then the overflow detector 15 can sense the positive and negative overflow states by using carry signals of two highest-order bits of the ALU 14. However, when the barrel shifter 11 is connected between the input and the ALU 14, as shown in FIG. 1, then the method described above is not adequate to detect the overflow condition.
During operation of the DSP of FIG. 1, a first 32 bit operand input to a left input LEFT is converted to 40 bits by barrel shifter 11 and a second 32 bit operand input to a right input RIGHT is converted to 40 bits through code extender 13. The resulting 40 bit operands are input to the 40-bit ALU 14. When ALU 14 operates in saturation mode, then a 40 bit result is generated from the ALU 14 and is output to multiplexer 32 where the 40 bit result from ALU 14 is converted into 32 bits under the control of overflow detector 15. A 32-bit saturated result appears at the output of multiplexer 17. It is typical in DSPs that the number of bits of the ALU 14 is larger than the effective number of bits of the DSP.
A special barrel shifter is needed to sense the overflow for a portion of the result which is completely lost, but in most applications it is sufficient to sense the overflow of only the 40 bits of the result from the ALU 14. Therefore, overflow detector 15 senses overflow using the nine high-order bits (39:31) of the result from the ALU 14 and, responsive thereto, controls the multiplexer 17.
However, since the barrel shifter 11 and the ALU 14 form a critical path in the DSP, additional processing of the result from the ALU 14 degrades the performance of the DSP.
FIG. 2 illustrates another conventional overflow detection system used in the D950 core from SGS-Thomson. The overflow condition is detected in the DSP of FIG. 2 by using carry signals C30 and C31 from the ALU 14. However, since the overflow is sensed only by examining two high-order bits of the ALU without detecting an actual overflow, the actual result from the barrel shifter 11 is disregarded in determining whether an overflow has occurred.